1. Field of the Invention
The present invention relates generally to semiconductor memories and, more particularly, to operation of memory cells.
2. Description of Related Art
Non-volatile semiconductor memory devices are designed to maintain programmed information even in the absence of electrical power. Non-volatile memories in common use today include read-only memories (ROMs) that typically are programmed to store a fixed bit pattern at the time of manufacture and that cannot be reprogrammed subsequently. Programmable read-only memories (PROMs) are a form of field-programmable memory devices that can be programmed once by a PROM programmer. Erasable programmable read-only memories (EPROMs) are programmable like PROMs, but can also be erased, for example, by exposure to ultraviolet light that places all bits in the memory to a known state (e.g., a logic 1). Electrically erasable programmable read-only memories (EEPROMs) are similar to EPROMs except that individual stored bits can be erased electrically. A particular form of EEPROMs, known as flash memories, typically is erased in blocks, although flash memory cells can be programmed individually.
Charge-trapping memory devices represent a relatively recent development in non-volatile memory technology. A charge-trapping memory cell normally is programmed by applying programming voltages to terminals of the device, which injects charge into a charge-trapping layer of the memory cell and modifies a threshold voltage (Vt) of the cell. The cell can be read by applying a reading voltage to the terminals of the device and detecting a level of current in a drain circuit, thereby inferring a value for the Vt of the cell. When the Vt is programmable to a value in one of two distinguishable ranges, then the cell is able to store a bit of information in a single transistor. Typically, the cell can assume one of two states: programmed and unprogrammed. An unprogrammed cell can have a Vt near about 2 V, while the Vt of a programmed cell might range from about 3 V to about 5 V, as an example. A cell that supports two distinguishable levels of Vt is referred to as a single-level cell (SLC).
Certain types of SLCs store a bit in each of two (i.e., left and right) localized regions of the charge-trapping layer, whereby Vt is modified separately in each of the two localized regions for a total of two (i.e., left and right) bits per transistor. Known methods of programming and reading SLCs are described in, for example, U.S. Pat. No. 6,011,725, which is incorporated herein in its entirety by reference.
Unfortunately, a degree of coupling, which has been referred to as a second-bit effect, almost inevitably exists between the left and right localized regions in a charge-trapping SLC. This coupling, which can raise the Vt of an unprogrammed region when the other region in the same cell is programmed, reduces a programming window associated with the cell. That is, the coupling effect can require that the Vt of a programmed region be increased to compensate for the coupling. The larger required Vt can lead to one or more of a larger supply voltage, a larger second-bit effect and other undesirable conditions that can reduce efficiency of operation of the cell. Prior-art approaches, seeking to rectify the second-bit effect by decoupling the charge distribution of the left bit from the charge distribution of the right bit, have met with only limited or qualified success.
A need thus exists in the prior art for a method of operating trapped-charge memory cells capable of mitigating the undesirable second-bit effect.